The present invention relates to a data signal line driving circuit of a digital matrix image display device using a digital image signal as an input signal, and an image display device including the same.
It is conventionally common that AC driving is performed in a matrix image display device using scanning and data signal lines, such as an active-matrix liquid crystal display device. Among this kind of image display devices, the majority of digital image display devices using a digital image signal as an input signal, in order to perform AC driving, include a voltage follower compatible with both positive and negative polarities at a stage immediately after a D/A converter with respect to each data signal line in a data signal line driving circuit. However, in the case of using the voltage follower (an output amplifier) in that manner, the D/A converter should inevitably make itself compatible with both voltage ranges of the positive and negative polarities, that increases circuit scale. Given this, such an arrangement is disclosed in Japanese Unexamined Patent Publication No. 26765/1997 (Tokukaihei 9-26765 published on Jan. 28, 1997) that a processor having a positive polarity output amplifier and a processor having a negative polarity output amplifier are provided to two adjacent data signal lines, respectively, an input source to each processor and a destination of output from each processor are switched so that the data signal lines have different polarities. Further, the same arrangement is disclosed in Japanese Unexamined Patent Publication No. 10075/2000 (Tokukai 2000-10075 published on Jan. 14, 2000) and Japanese Unexamined Patent Publication No. 281930/1997 (Tokukaihei 9-281930 published on Oct. 31, 1997).
Further, Japanese Unexamined Patent Publication No. 73164/1999 (Tokukaihei 11-73164 published on Mar. 16, 1999) discloses an arrangement such that on upper and lower sides of a liquid crystal panel are respectively provided data signal line driving circuits with output buffers, one of which is used for the positive polarity and the other for the negative polarity, and connection can be switched so that, when either one of the data signal line driving circuits drives the odd-numbered data signal lines, the other drives the even-numbered data signal lines. Further, Japanese Unexamined Patent Publication No. 137443/1996 (Tokukaihei 8-137443 published on May 31, 1996) discloses an arrangement in which on upper and lower sides of a pixel array are respectively provided data signal line driving circuits, each including a positive polarity amplifier and a negative polarity amplifier, one of which drives the odd-numbered data signal lines and the other drives the even-numbered data signal lines so that they have different polarities and that the polarity reverses by field.
An image display device for a battery-driven device, the representative of which is a latest mobile information terminal, is required to reduce power consumption so that long-hour use can be attained. However, the foregoing data signal line driving circuit having the voltage followers has a problem that the large sum of bias currents increases power consumption.
In addition, the presence of numbers of digital image signal processors with voltage followers inevitably increases the circuit scale of the data signal line driving circuit, that raises another problem of being incompatible with high-resolution image display devices.
It is an object of the present invention to provide a data signal line driving circuit capable of low power consumption while having voltage followers, and an image display device including the same. Another object of the present invention is to provide a data signal line driving circuit capable of attaining a high-resolution image display device in addition to the first object, and an image display device including the same.
In order to attain the foregoing object, a data signal line driving circuit according to the present invention, which outputs an analog video signal to each of data signal lines of an image display device having scanning signal lines and the data signal lines via a voltage follower according to such a polarity relation that a polarity of a voltage with respect to a predetermined voltage of the adjacent data signal lines is reversed while reversing the polarity of the voltage of the single data signal line by a predetermined period, the analog video signal being obtained from an inputted digital video signal through D/A conversion, the data signal line driving circuit includes: a positive polarity system including a positive polarity D/A converter and a positive polarity voltage follower in the case of the polarity of the voltage, and a negative polarity system including a negative polarity D/A converter and a negative polarity voltage follower; selection circuits; and a switch circuit, wherein: both the positive polarity system and the negative polarity system are provided with respect to each set of the data signal lines consisting of a predetermined number of the consecutive data signal lines which are not less than three data signal lines, a range of a power voltage of the positive polarity voltage follower is a high voltage side half of a range of a power voltage of a positive/negative polarity-compatible voltage follower, and a range of a power voltage of the negative polarity voltage follower is a low voltage side half of the range of the power voltage of the positive/negative polarity-compatible voltage follower, the selection circuits each divide and selectively input the each digital video signal to the positive polarity system or negative polarity system in one scanning period so as to satisfy the polarity relation, and the switch circuit switches paths so that respective output signals of the voltage followers are outputted in parallel in order of the corresponding data signal lines.
With this arrangement, both the positive and negative polarity systems are provided with respect to each set of a predetermined number of the consecutive data signal lines which are not less than three data signal lines, and the selection circuits successively selectively input a plurality of digital video signals to be inputted for one set with respect to the respective systems in one scanning period, and the switch circuit outputs output signals of the respective voltage followers in parallel in order of the corresponding data signal lines. Furthermore, the voltage followers are separately provided for positive polarity use and for negative polarity use, and the ranges of power voltages thereof are respectively the high voltage side half and the low voltage side half of the range of a power voltage of a positive/negative polarity-compatible voltage follower.
This arrangement enables processing of all the digital video signals for input while allowing the voltage followers to be provided so that the total number of the voltage followers for a set of data signal lines is smaller than the total number of the set of data signal lines. Therefore, compared with the case where all data signal lines are provided with the voltage followers, the total number of the voltage followers is reduced while suppressing bias currents of the respective voltage followers. Accordingly, the sum total of bias currents of the voltage followers becomes small.
As discussed, it is possible to provide the data signal line driving circuit capable of low power consumption while having the voltage followers.
Further, since the number of systems which performs processing of the digital video signals to be inputted is decreased, it is possible to drive an image display device having a data signal line of a smaller pitch, thereby attaining a high-resolution image display device as well.
In addition to the foregoing arrangement, it is preferable that both the positive and negative polarity systems are provided with respect to each set of a predetermined even number of the consecutive data signal lines.
With this arrangement, since one set of the data signal lines consists of a predetermined even number of the data signal lines which are not less than four data signal lines, the positive and negative polarity systems can be used simultaneously. Consequently, when either one of the systems is in use, the other is free from standby power consumption, thereby greatly reducing power consumption.
Further, in addition to the foregoing arrangement, it is preferable that both the positive and negative polarity systems are provided with respect to each set of the data signal lines consisting of the data signal lines for two pixels, where one pixel is made up of three subpixels R, G and B which are adjacently disposed in a direction of the scanning signal line.
With this arrangement, since both the positive and negative polarity systems are provided with respect to each set of the data signal lines consisting of the data signal lines for two pixels, the operation of selective to input by the selection circuits and the operation of switch by the switch circuit can readily be performed in the color of R, G or B. Moreover, it is possible to attain a data signal line driving circuit with the enhanced general versatility which can be mounted in a common color image display device.
Further, in addition to the foregoing arrangement, it is preferable to include either one of the data signal line driving circuits and demultiplexers which switch connection paths between an output terminal of the switch circuit and the data signal line so that an output signal of the data signal line driving circuit is outputted to the corresponding data signal line.
With this arrangement, an image is displayed by thus outputting the output signal of the data signal line driving circuit to the corresponding data signal line by the demultiplexers. Therefore, in the case where analog video signals are chronologically divided and outputted from the switch circuit in one scanning period, the analog video signals can be distributed to the corresponding data signal lines with ease, while making it possible to provide an image display device capable of low power consumption.